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https://github.com/KhronosGroup/OpenCL-CTS.git
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4e3f16b2b9
Unlike related PR #2344 that simply warns about unsupported FTZ, this PR attempts to correctly handle FTZ on RISC-V. RISC-V 'f' extension does not support any way to enable/disable flushing subnormals to zero, implementations are required to always support subnormals. Therefore this PR re-uses FTZ handling code from PPC, where flushing also has to be explicitly performed.
146 lines
5.0 KiB
C++
146 lines
5.0 KiB
C++
//
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// Copyright (c) 2017 The Khronos Group Inc.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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#ifndef _fpcontrol_h
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#define _fpcontrol_h
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#include <cstdint>
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// In order to get tests for correctly rounded operations (e.g. multiply) to
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// work properly we need to be able to set the reference hardware to FTZ mode if
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// the device hardware is running in that mode. We have explored all other
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// options short of writing correctly rounded operations in integer code, and
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// have found this is the only way to correctly verify operation.
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//
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// Non-Apple implementations will need to provide their own implentation for
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// these features. If the reference hardware and device are both running in the
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// same state (either FTZ or IEEE compliant modes) then these functions may be
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// empty. If the device is running in non-default rounding mode (e.g. round
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// toward zero), then these functions should also set the reference device into
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// that rounding mode.
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#if defined(__APPLE__) || defined(_MSC_VER) || defined(__linux__) \
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|| defined(__MINGW32__)
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#ifdef _MSC_VER
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typedef int FPU_mode_type;
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#else
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typedef int64_t FPU_mode_type;
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#endif
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#if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) \
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|| defined(_M_X64) || defined(__MINGW32__)
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#include <xmmintrin.h>
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#elif defined(_M_ARM64)
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#include <intrin.h>
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#elif defined(__PPC__)
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#include <fpu_control.h>
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extern __thread fpu_control_t fpu_control;
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#elif defined(__riscv)
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#define _FPU_MASK_NI 1
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static FPU_mode_type fpu_control;
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#elif defined(__mips__)
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#include "mips/m32c1.h"
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#endif
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// Set the reference hardware floating point unit to FTZ mode
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inline void ForceFTZ(FPU_mode_type *oldMode)
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{
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#if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) \
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|| defined(_M_X64) || defined(__MINGW32__)
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*oldMode = _mm_getcsr();
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_mm_setcsr(*oldMode | 0x8040);
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#elif defined(__PPC__) || defined(__riscv)
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*oldMode = fpu_control;
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fpu_control |= _FPU_MASK_NI;
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#elif defined(__arm__)
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unsigned fpscr;
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__asm__ volatile("fmrx %0, fpscr" : "=r"(fpscr));
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*oldMode = fpscr;
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__asm__ volatile("fmxr fpscr, %0" ::"r"(fpscr | (1U << 24)));
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// Add 64 bit support
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#elif defined(__aarch64__) // Clang
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uint64_t fpscr;
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__asm__ volatile("mrs %0, fpcr" : "=r"(fpscr));
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*oldMode = fpscr;
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__asm__ volatile("msr fpcr, %0" ::"r"(fpscr | (1U << 24)));
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#elif defined(_M_ARM64) // Visual Studio
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uint64_t fpscr;
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fpscr = _ReadStatusReg(ARM64_FPSR);
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*oldMode = fpscr;
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_WriteStatusReg(ARM64_FPCR, fpscr | (1U << 24));
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#elif defined(__mips__)
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fpa_bissr(FPA_CSR_FS);
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#else
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#error ForceFTZ needs an implentation
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#endif
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}
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// Disable the denorm flush to zero
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inline void DisableFTZ(FPU_mode_type *oldMode)
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{
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#if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) \
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|| defined(_M_X64) || defined(__MINGW32__)
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*oldMode = _mm_getcsr();
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_mm_setcsr(*oldMode & ~0x8040);
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#elif defined(__PPC__) || defined(__riscv)
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*oldMode = fpu_control;
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fpu_control &= ~_FPU_MASK_NI;
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#elif defined(__arm__)
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unsigned fpscr;
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__asm__ volatile("fmrx %0, fpscr" : "=r"(fpscr));
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*oldMode = fpscr;
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__asm__ volatile("fmxr fpscr, %0" ::"r"(fpscr & ~(1U << 24)));
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// Add 64 bit support
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#elif defined(__aarch64__) // Clang
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uint64_t fpscr;
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__asm__ volatile("mrs %0, fpcr" : "=r"(fpscr));
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*oldMode = fpscr;
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__asm__ volatile("msr fpcr, %0" ::"r"(fpscr & ~(1U << 24)));
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#elif defined(_M_ARM64) // Visual Studio
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uint64_t fpscr;
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fpscr = _ReadStatusReg(ARM64_FPSR);
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*oldMode = fpscr;
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_WriteStatusReg(ARM64_FPCR, fpscr & ~(1U << 24));
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#elif defined(__mips__)
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fpa_bicsr(FPA_CSR_FS);
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#else
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#error DisableFTZ needs an implentation
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#endif
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}
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// Restore the reference hardware to floating point state indicated by *mode
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inline void RestoreFPState(FPU_mode_type *mode)
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{
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#if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) \
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|| defined(_M_X64) || defined(__MINGW32__)
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_mm_setcsr(*mode);
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#elif defined(__PPC__) || defined(__riscv)
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fpu_control = *mode;
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#elif defined(__arm__)
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__asm__ volatile("fmxr fpscr, %0" ::"r"(*mode));
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// Add 64 bit support
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#elif defined(__aarch64__) // Clang
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__asm__ volatile("msr fpcr, %0" ::"r"(*mode));
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#elif defined(_M_ARM64) // Visual Studio
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_WriteStatusReg(ARM64_FPCR, *mode);
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#elif defined(__mips__)
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// Mips runs by default with DAZ=1 FTZ=1
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#else
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#error RestoreFPState needs an implementation
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#endif
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}
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#else
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#error ForceFTZ and RestoreFPState need implentations
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#endif
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#endif |