A 3D required work-group size is always valid, but a 1D or 2D required
work-group size is only valid when the work-group size in those
dimensions is equal to one.
fixes#2575
see #2501
This tests the following scenarios:
1. Execute a kernel with a required work-group size, passing `NULL` as
the local work size.
2. Query the suggested work-group size for a kernel with a required
work-group size.
test_error returns the err given as the first argument. As the
run_test function returns a bool, we end up returning true (meaning
pass) when an api function fails.
Instead return explicitly false (meaning fail).
* Improve Functionality of Harness
In the harness we previously were able to determine whether or
not a device supports the half or double data types, but doing so
required unintuitive function calls and would need to be repeated
per test.
A new pair of functions have been added which clearly state
what they do, and makes it easier to determine whether or not
a device supports the types.
Signed-off-by: Chetankumar Mistry <chetan.mistry@arm.com>
* Add Test for CL_KERNEL_ATTRIBUTES (#832)
This test generates dummy kernels which have any
permutation combining the following attributes:
* vec_type_hint
* work_group_size_hint
* reqd_work_group_size
It then gets the attributes by using clGetKernelInfo
and validates that the attributes returned are correct.
By matching the attributes which were used to generate
the kernel are present in the returned string from
clGetKernelInfo.
This test has been implemented as part of the
test_conformance/api suite.
Signed-off-by: Chetankumar Mistry <chetan.mistry@arm.com>
* [SQUASH] Remove Signed Vector Attribute Hints
As per comments, SPIR-V does not distinguish the signedness
of an argument. This change removes the "signed" types
to ensure that the test passes in all scenarios.
Signed-off-by: Chetankumar Mistry <chetan.mistry@arm.com>
* [SQUASH] Add TODO for Signed Vector Hints
As the current version only tests for unsigned
vector types (uchar/uint/etc), add a TODO in the code
as a reference to future work to introduce signed vector
tests
Signed-off-by: Chetankumar Mistry <chetan.mistry@arm.com>
