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initial RISC-V support (#2614)
Unlike related PR #2344 that simply warns about unsupported FTZ, this PR attempts to correctly handle FTZ on RISC-V. RISC-V 'f' extension does not support any way to enable/disable flushing subnormals to zero, implementations are required to always support subnormals. Therefore this PR re-uses FTZ handling code from PPC, where flushing also has to be explicitly performed.
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@@ -859,7 +859,9 @@ double reference_add(double x, double y)
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__m128 vb = _mm_set_ss((float)b);
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va = _mm_add_ss(va, vb);
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_mm_store_ss((float *)&a, va);
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#elif defined(__PPC__)
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#elif defined(__PPC__) || defined(__riscv)
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// RISC-V CPUs with default 'f' fp32 extension do not support any way to
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// enable/disable FTZ mode, subnormals are always handled without flushing.
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// Most Power host CPUs do not support the non-IEEE mode (NI) which flushes
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// denorm's to zero. As such, the reference add with FTZ must be emulated in
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// sw.
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@@ -876,7 +878,7 @@ double reference_add(double x, double y)
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} ub;
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ub.d = b;
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cl_uint mantA, mantB;
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cl_ulong addendA, addendB, sum;
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cl_ulong addendA, addendB;
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int expA = extractf(a, &mantA);
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int expB = extractf(b, &mantB);
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cl_uint signA = ua.u & 0x80000000U;
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@@ -972,7 +974,7 @@ double reference_multiply(double x, double y)
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__m128 vb = _mm_set_ss((float)b);
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va = _mm_mul_ss(va, vb);
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_mm_store_ss((float *)&a, va);
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#elif defined(__PPC__)
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#elif defined(__PPC__) || defined(__riscv)
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// Most Power host CPUs do not support the non-IEEE mode (NI) which flushes
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// denorm's to zero. As such, the reference multiply with FTZ must be
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// emulated in sw.
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@@ -3351,7 +3353,7 @@ long double reference_cbrtl(long double x)
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long double reference_rintl(long double x)
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{
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#if defined(__PPC__)
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#if defined(__PPC__) || defined(__riscv)
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// On PPC, long doubles are maintained as 2 doubles. Therefore, the combined
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// mantissa can represent more than LDBL_MANT_DIG binary digits.
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x = rintl(x);
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