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initial RISC-V support (#2614)
Unlike related PR #2344 that simply warns about unsupported FTZ, this PR attempts to correctly handle FTZ on RISC-V. RISC-V 'f' extension does not support any way to enable/disable flushing subnormals to zero, implementations are required to always support subnormals. Therefore this PR re-uses FTZ handling code from PPC, where flushing also has to be explicitly performed.
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@@ -191,7 +191,7 @@ double sse_mul_sd(double x, double y)
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}
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#endif
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#ifdef __PPC__
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#if defined(__PPC__) || defined(__riscv)
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float ppc_mul(float a, float b)
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{
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float p;
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@@ -630,9 +630,11 @@ test_status InitCL( cl_device_id device )
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// turn that off
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f3[i] = sse_mul(q, q2);
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f4[i] = sse_mul(-q, q2);
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#elif defined(__PPC__)
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// None of the current generation PPC processors support HW
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// FTZ, emulate it in sw.
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#elif (defined(__PPC__) || defined(__riscv))
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// RISC-V CPUs with default 'f' fp32 extension do not support
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// enabling/disabling FTZ mode, subnormals are always handled
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// without FTZ. None of the current generation PPC processors
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// support HW FTZ, emulate it in sw.
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f3[i] = ppc_mul(q, q2);
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f4[i] = ppc_mul(-q, q2);
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#else
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@@ -721,9 +723,10 @@ test_status InitCL( cl_device_id device )
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skipTest[j][i] = (bufSkip[i] ||
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(gSkipNanInf && (FE_OVERFLOW == (FE_OVERFLOW & fetestexcept(FE_OVERFLOW)))));
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#if defined(__PPC__)
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// Since the current Power processors don't emulate flush to zero in HW,
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// it must be emulated in SW instead.
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#if defined(__PPC__) || defined(__riscv)
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// Since the current Power processors don't emulate flush to
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// zero in HW, it must be emulated in SW instead. (same for
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// RISC-V CPUs with 'f' extension)
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if (gForceFTZ)
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{
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if ((fabsf(correct[j][i]) < FLT_MIN) && (correct[j][i] != 0.0f))
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@@ -760,7 +763,6 @@ test_status InitCL( cl_device_id device )
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}
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}
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double *f = (double*) buf1;
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double *f2 = (double*) buf2;
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double *f3 = (double*) buf3_double;
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